SOM : A Recon gurable Neural Network Architecture Basedon Bit Stream

We introduce the RAN 2 SOM (Reconngurable Architecure Neural Networks with Serially Operating Multipliers) architecture, a neural net architecture with a reconngurable interconnection scheme based on bit stream arithmetic. RAN 2 SOM nets are implemented using eld programmable gate array logic. By conducting the training phase in software and executing the actual application in hardware, connicting demands can be met: training beneets from a fast edit-debug cycle, and once the design has stabilized, a hardware implementation results in higher performance. While neural nets have been implemented in hardware in the past, larger digital nets have not been possible due to the real-estate requirements of single neu-rons. We present a bit-serial encoding scheme and computation model, which allows space-eecient computation of the sum of weighted inputs, thereby facilitating the implementation of complex neural networks .